1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory such as a ferroelectric memory (FRAM, FeRAM).
2. Description of the Related Art
An FRAM (ferroelectric random access memory) which uses ferroelectric capacitances for memory cells can retain data when power supply is cut off. Thus, the FRAM is applied to IC cards, a storage medium of game machines and other devices. A technique associated with the FRAM is disclosed in Japanese Unexamined Patent Application Publication No. 2005-129151, for example.
FIG. 1 illustrates an FRAM of prior art. FIG. 2 shows a memory cell of the FRAM in FIG. 1. As illustrated in FIG. 1, an FRAM 500 includes an address input buffer 502, an address decoder 504, a memory cell array 506, a sense amplifier 508, a write amplifier 510, and a data input/output buffer 512.
The address input buffer 502 receives an external input address inputted to address input pins AD0 through ADi-1 (i: natural number) and outputs the external input address to the address decoder 504 in read and write operations. The address decoder 504 selects one of plural rows in the memory cell array 506 based on the external input address (address supplied from the address input buffer 502) in the read and write operations.
The memory cell array 506 has a plurality of memory cells MC arranged in matrix at the cross points of plural word lines WL and plural plate lines PL and m pairs of bit lines BL and BLX (m: natural number). The memory cells MC are complementary memory cells called 2T2C type as illustrated in FIG. 2, for example, and have transfer transistors (nMOS transistors) N1 and N2 and ferroelectric capacitances F1 and F2. The transfer transistor N1 and the ferroelectric capacitance F1 are connected in series between the bit line BL and the plate line PL. The transfer transistor N2 and the ferroelectric capacitance F2 are connected in series between the bit line BLX and the plate line PL. The gates of the transfer transistors N1 and N2 are connected with the word line WL.
As illustrated in FIG. 1, the sense amplifier 508 reads data from a selected row (row selected by the address decoder 504) in the memory cell array 506 in the read operation. The write amplifier 510 writes back the data read by the sense amplifier 508 to the selected row in the memory cell array 506 in the read operation. The write amplifier 510 writes external input data (data supplied from the data input/output buffer 512) to the selected row in the memory cell array 506 in the write operation. The data input/output buffer 512 receives data read by the sense amplifier 508 and outputs the data to data input/output pins DQ0 through DQm-1 as external output data in the read operation. The data input/output buffer 512 receives external input data inputted to the data input/output pins DQ0 through DQm-1 and outputs the external input data to the write amplifier 510 in the write operation.
In the FRAM 500 having this structure, when an external input address is inputted to the address input pins AD0 through ADi-1 in the read operation, the external input address is supplied to the address decoder 504 via the address input buffer 502. Then, the row corresponding to the external input address is selected from the plural rows in the memory cell array 506. Subsequently, data is read from the selected row of the memory cell array 506 by the sense amplifier 508, and the data thus read out is outputted to the data input/output pins DQ0 through DQm-1 via the data input/output buffer 512 as external output data. The data read by the sense amplifier 508 is written back to the selected row in the memory cell array 506 by the write amplifier 510.
When an external input address is inputted to the address input pins AD0 through ADi-1 in the write operation similarly to the read operation, the external input address is supplied to the address decoder 504 via the address input buffer 502. Then, the row corresponding to the external input address is selected from the plural rows in the memory cell array 506. Subsequently, external input data inputted to the data input/output pins DQ0 through DQm-1 and supplied via the data input/output buffer 512 is written to the selected row in the memory cell array 506 by the write amplifier 510.
In the FRAM, the write operation polarizes ferroelectric capacitances constituting the memory cell as an access target by applying positive voltage or negative voltage thereto, while the read operation detects the presence or absence of reverse polarization charge by applying positive voltage to the ferroelectric capacitances constituting the memory cell as the access target. In the write operation, though not shown in detail in FIGS. 1 and 2, the word line WL is activated to a high level and the transfer transistor N1 is turned on in the memory cell MC as the access target (m memory cells MC in the row selected by the address decoder 504), and positive voltage or negative voltage is applied between the bit line BL and the plate line PL, so as to apply positive voltage or negative voltage to the ferroelectric capacitance F1 and write desired data. More specifically, when “0” data is written to the ferroelectric capacitance F1, the bit line BL is set to the ground voltage GND (0V) and the plate line PL is set to the power supply voltage VDD. When “1” data is written to the ferroelectric capacitance F1, the bit line BL is set to the power supply voltage VDD and the plate line PL is set to the ground voltage GND. Data having reverse logic of that of the data written to the ferroelectric capacitance F1 is written to the ferroelectric capacitance F2 by the similar method. When voltage applied to the ferroelectric capacitances F1 and F2 is removed after completion of the write operation, the polarization of the ferroelectric capacitances F1 and F2 is maintained. Thus, the data written to the ferroelectric capacitances F1 and F2 is retained as non-volatile data.
In the read operation, the word line WL is activated to a high level and the transfer transistor N1 is turned on in the memory cell MC as the access target, and the plate line PL is set to the power supply voltage VDD. The bit line BL is pre-charged to the ground voltage GND. When the plate line PL is set to the power source voltage VDD, positive voltage is applied to the ferroelectric capacitance F1. When the ferroelectric capacitance F1 has “0” data having been written thereto in this step, relatively small charge flows through the bit line BL without causing reverse polarization since the polarity of the voltage applied to the ferroelectric capacitance F1 in the read operation is the same as the polarity of the voltage applied thereto in the write operation. When the ferroelectric capacitance F1 has “1” data having been written thereto, relatively large charge flows through the bit line BL causing reverse polarization since the polarity of the voltage applied to the ferroelectric capacitance F1 in the read operation is the opposite polarity to that of the voltage applied thereto in the write operation. Then, read data of the ferroelectric capacitance F1 is generated by detecting the charge flowing through the bit line BL by the sense amplifier 508. In the ferroelectric capacitance F2, read data having the complementary logic of that of the read data of the ferroelectric capacitance F1 is generated by the similar method.
In the FRAM, positive voltage is applied to the ferroelectric capacitance constituting the memory cell as the access target in the read operation. Thus, data read from the ferroelectric capacitance is equivalent to “0” data write thereto, and is so-called “destructive read”. As a result, “0” data is written to the ferroelectric capacitance to which ‘1’ data has been written in the memory cell as the access target in the read operation, and it is therefore necessary to write back the “1” data to the ferroelectric capacitance.
Generally, the possible number of data rewrites to the ferroelectric capacitance is limited due to the limitations of the ferroelectric material, and is approximately 1 E10 at the largest. In the FRAM, it is necessary to write back “1” data to the ferroelectric capacitance constituting the memory cell as the access target in the read operation when the ferroelectric capacitance has “1” data having been written thereto. Thus, data write to the ferroelectric capacitance is required not only in the write operation but also in the read operation. As a result, the FRAM has greater limitations for use than semiconductor memories such as SRAM (static RAM) and DRAM (dynamic RAM), which can perform access operation (read operation and write operation) without limitation. It is therefore demanded to develop a technique enabling reduction in the number of repetitive data writes required in the read operation in the non-volatile semiconductor memory (such as FRAM) so that a life of the non-volatile semiconductor memory can be prolonged.